From b982a5bea4273a4b9fc007d5046bed8d1669c07f Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Mon, 19 Sep 2016 11:37:09 +0200 Subject: [PATCH] x86/Intel: hide CPUID faulting capability from guests We don't currently emulate it, so guests should not be misguided to believe they can (try to) use it. For now, simply return zero to guests for platform MSR reads, and only accept (by discarding) writes of zero. If ever there will be bits we can safely expose to guests, let's handle them by white listing. (As a side note - according to SDM version 059 bit 31 is reserved on all known families.) Reported-by: Kyle Huey Signed-off-by: Jan Beulich Acked-by: Andrew Cooper Acked-by: Kevin Tian --- xen/arch/x86/hvm/vmx/vmx.c | 14 ++++++++++++++ xen/arch/x86/traps.c | 16 ++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 2759e6f31e..50cbfed4dc 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -2699,6 +2699,13 @@ static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content) if ( vpmu_do_rdmsr(msr, msr_content) ) goto gp_fault; break; + + case MSR_INTEL_PLATFORM_INFO: + if ( rdmsr_safe(MSR_INTEL_PLATFORM_INFO, *msr_content) ) + goto gp_fault; + *msr_content = 0; + break; + default: if ( passive_domain_do_rdmsr(msr, msr_content) ) goto done; @@ -2918,6 +2925,13 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content) if ( vpmu_do_wrmsr(msr, msr_content, 0) ) goto gp_fault; break; + + case MSR_INTEL_PLATFORM_INFO: + if ( msr_content || + rdmsr_safe(MSR_INTEL_PLATFORM_INFO, msr_content) ) + goto gp_fault; + break; + default: if ( passive_domain_do_wrmsr(msr, msr_content) ) return X86EMUL_OKAY; diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index b24ca74dce..24d173ff8a 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -2938,6 +2938,14 @@ static int emulate_privileged_op(struct cpu_user_regs *regs) if ( v->arch.debugreg[7] & DR7_ACTIVE_MASK ) wrmsrl(regs->_ecx, msr_content); break; + + case MSR_INTEL_PLATFORM_INFO: + if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || + msr_content || + rdmsr_safe(MSR_INTEL_PLATFORM_INFO, msr_content) ) + goto fail; + break; + case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7): case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL(3): case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2: @@ -3066,6 +3074,14 @@ static int emulate_privileged_op(struct cpu_user_regs *regs) /* No extra capabilities are supported */ regs->eax = regs->edx = 0; break; + + case MSR_INTEL_PLATFORM_INFO: + if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || + rdmsr_safe(MSR_INTEL_PLATFORM_INFO, val) ) + goto fail; + regs->eax = regs->edx = 0; + break; + case MSR_P6_PERFCTR(0)...MSR_P6_PERFCTR(7): case MSR_P6_EVNTSEL(0)...MSR_P6_EVNTSEL(3): case MSR_CORE_PERF_FIXED_CTR0...MSR_CORE_PERF_FIXED_CTR2: -- 2.30.2